Efficient FPGA implementation and verification of difference expansion based reversible watermarking with improved time and resource utilization期刊界 All Journals 搜尽天下杂志传播学术成果专业期刊搜索期刊信息化学术搜索

Efficient FPGA implementation and verification of difference expansion based reversible watermarking with improved time and resource utilization

Affiliation:	1. Department of Electronics and Instrumentation Engineering, National Institute of Technology, Silchar, 788010, India;2. Department of Electronics and Communication Engineering, Mizoram University (A Central University), Aizawl, 796 004, India;1. School of Economics and Management, Xi''an University of Technology, Xi''an, Shaanxi, 710048, China;2. Business School, Xinxiang University, Xinxiang, Henan, 453003, China;1. Department of Pediatrics, Tengzhou Central People''s Hospital, Tengzhou, Shandong, 277500, China;2. Children''s Intensive Care Unit, Tengzhou Central People''s Hospital, Tengzhou, Shandong, 277500, China;3. Pharmacy Department, Tengzhou Central People''s Hospital, Tengzhou, Shandong, 277500, China;1. College of Foreign Languages, Beihua University, Jilin, Jilin, 132013, China;2. General Office, Jilin Engineering Normal University, Changchun, Jilin, 130052, China;1. School of Journalism and Communication, Hunan University, Changsha, Hunan, 410082, China;2. Faculty of Artificial Intelligence in Education, Central China Normal University, Wuhan, Hubei, 430079, China;3. Hunan Broadcasting System Group Co., Ltd., Changsha, Hunan, 410000, China

Abstract:	This paper presents Xilinx System Generator (XSG) model design for realization of reversible watermarking algorithm using Difference Expansion (DE) approach in System-On-Chip (SoC) Field Programmable Gate Array (FPGA) environment. The reversible watermarking is verified by taking a (4 × 4) sized test image and is applicable for larger sizes of cover images. The outcomes of the result demonstrate that the proposed structural design allows combining MATLAB-Simulink and XSG during graphical user interface for image processing applications. The superiority of the algorithm is justified by using comparative analysis with some well-known methods in both software and hardware environments. The method provides effectively higher PSNR at higher embedding capacity. It is also found that the method requires less time and hardware resources with throughput of 13.516 Mb/s at operational frequency of 80 MHz for real time implementation using FPGA.

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