Low power time-domain rail-to-rail comparator with a new delay element for ADC applications

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step.