A 75-dB image rejection IF-input quadrature-sampling SC /spl Sigma//spl Delta/ Modulator

Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) /spl Sigma//spl Delta/ modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-/spl mu/m CMOS process with an active area of 0.57mm/sup 2/. The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 200-kHz signal bandwidth.