Reconfiguring fault-tolerant two-dimensional array architectures |
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| Authors: | Davis NJ IV Gray FG Wegner JA Lawson SE Murthy V White TS |
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| Affiliation: | Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA; |
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| Abstract: | Circuit complexities reduce overall reliability and mean-time-between-failure rates of today's very large processing arrays. Our integrated, three-level hierarchy of reconfiguration methods provides reasonable levels of fault tolerance for such systems. Operating in a completely distributed fashion, the hierarchy does not require that any components be fault free. It significantly improves array reliability by using a combination of transient fault rollback techniques and local and global reconfiguration algorithms |
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