Resource efficient implementation of T-Boxes in AES on Virtex-5 FPGA |
| |
Authors: | Dur-e-Shahwar Kundi Arshad Aziz |
| |
Affiliation: | Electrical Engineering Department, National University of Science and Technology (NUST), Habib Rehmatullah Road, Karachi-75350, Pakistan |
| |
Abstract: | This work presents a resource efficient implementation of T-Box module of Advanced Encryption Standard (AES) on Xilinx's Virtex-5 Field Programmable Gate Array (FPGA). The proposed architecture utilizes the 100% capacity of FPGA's dedicated Block RAM (BRAM) as compared to conventional techniques, where the consumption of BRAM memory is from 25% to 50%. The results show that the module fits into 4 BRAMs, thus reducing on device resources by 50%. |
| |
Keywords: | Cryptography AES FPGA T-Box Virtex-5 |
本文献已被 ScienceDirect 等数据库收录! |