Design for Delay Testability in High-Speed Digital ICs |
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| Authors: | HG Kerkhoff H Speek M Shashani M Sachdev |
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| Affiliation: | (1) MESA+ Research Institute, University of Twente, Enschede, The Netherlands;(2) Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, N2L 3G1 |
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| Abstract: | The cost-effective testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, costly testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability (DfDT) technique such that high-speed ICs can be tested using inexpensive, low-speed test systems. Also extensions for possible full BIST of delay faults are addressed. |
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| Keywords: | delay-fault testing design for delay testability BIST high-speed testing |
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