Multiple-output parity bit signature for exhaustive testing |
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Authors: | Wen-Ben Jone Sunil R Das |
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Affiliation: | (1) Department of Computer Science, New Mexico Tech, 87801 Socorro, NM, USA;(2) Department of Electrical Engineering, University of Ottawa, KIN 6N5 Ottawa, Ontario, Canada |
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Abstract: | In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology. |
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Keywords: | Built-in self-test (BIST) design for testability test response analyzer |
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