A fast pipelined VLSI adder for fast trigger decisions at the Superconducting Super Collider

We present a four 12-bit binary number adder proposed for use in the computation of the pipelined energy sums of data from the detectors at the Superconducting Super Collider (SSC). It was fabricated using a 1.2 μm N-well CMOS process. It comprises three 12-bit adders organized as a two-stage pipeline. To compute the final carry of each of the 12-bit adders, we used the Carry-Select technique applied to their 4-bit adder subcells. The 4-bit adders used the Carry-Lookahead method to compute their carries. In order to reduce the circuit area and to simplify the structure of this application specific integrated circuit (ASIC) we employed a Multiple-Output Domino Logic design style. The first stage of the pipeline (two adders) performs two 12-bit additions in parallel while the second stage (one adder) finishes up the previously started computation. The pipeline is driven using a two-phase clocking strategy by processing a single-phase external clock. We achieved an worst case throughput of 18 ns. In the best case the throughput was 16.5 ns. We included a built-in facility for testing the first stage of the pipeline. The area of the circuit is 1425×5510 μm², it has 76 pads, and it is packed in a 132 pin grid array (PGA). The transistor count is 6639. The dissipated power at a 18-ns clock period was ≈ 0.75 W. The circuit has been fabricated through the MOSIS service. We found an yield of ≈ 80% for a lot of 50 chips.