Multiple twisted dataline techniques for multigigabit DRAMs

To provide reliable scaled DRAMs, new multiple twisted dataline techniques are proposed and analyzed. Their effectiveness in reducing both the bitline (BL) and wordline (WL) coupling noises in scaled DRAM's was evaluated by means of soft-error-rate measurements on 256-Mbit and 1-Gbit DRAM test chips. At the 1-Gbit level of integration, in our proposed scheme-compared to the conventional twisted bitline (TBL) scheme-the chip area penalty due to twisting is reduced by 66% and the BL coupling noise is reduced by 45%. At the 256-Mbit level, when the proposed technique is applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional TBL and WL schemes. Faster data access time can also be expected when the proposed technique is applied to BL and/or WL structures