Performance study of n-MOS natural transistor fabricated by low thermal budget process

Natural n-MOS transistor and MOS capacitor test structures have been fabricated by the low temperature process design for better control on device dimensions. Si-SiO₂ interface properties and performance of LPCVD gorwn polysilicon gate natural transistor has been studied through MOS C-V analysis and physical-electrical modeling. Transistor behavior at cryogenic temperatures has also been analysed through MOS C-V characteristics and one dimensional transport equations.