Functionally testable path delay faults on a microprocessor |
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| Authors: | Wei-Cheng Lai Krstic A. Kwang-Ting Cheng |
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| Affiliation: | Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA; |
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| Abstract: | The impact of delay defects on these functionally untestable paths on overall circuit performance involves identification of such paths determining the achievable path delay fault coverage and reducing the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable |
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