| 基于流水线重构技术的16x16位乘加器的设计 |
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| 引用本文： | 赵倩,汤乃云,韩桂泽.基于流水线重构技术的16x16位乘加器的设计[J].微计算机信息,2006(35). |
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| 作者姓名： | 赵倩 汤乃云 韩桂泽 |
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| 作者单位： | 上海电力学院电子科学与技术系，上海电力学院电子科学与技术系，上海大学微电子研究与开发中心 |
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| 基金项目： | 上海市重点学科建设项目资助(项目编号:P1303) |
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| 摘 要： | 比较了几种16x16位乘加器的实现方法,给出了一种嵌入于微处理器的基于流水线重构技术的16x16位乘加器的设计方案,该设计可完成16bit整数或序数的乘法或乘加运算,并提高了运算的速度,减少了面积。利用CadenceEDA工具对电路进行了仿真,仿真结果验证了设计的准确性。
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| 关 键 词： | 乘加器 乘法器 流水线 |
A pipelined 16x16-bit Multiplier Accumulator design |
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| Zhao Qian Tang Naiyun Han Guize.A pipelined 16x16-bit Multiplier Accumulator design[J].Control & Automation,2006(35). |
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| Authors: | Zhao Qian Tang Naiyun Han Guize |
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| Affiliation: | (Department of Electronic Science and Technology,Shanghai University of Electric Power,Shanghai,200090)Zhao Qian Tang Naiyun (Microelectronics R&D Center,Shanghai University,Shanghai 200072,China)Han Guize |
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| Abstract: | This paper compares some methods of 16x16 multiplier accumulator design, and describes a pipelined and reconstructed technology to achieve 16x16-bit multiplier accumulator embedded in an MCU (Micro-Control Unit). which supports both signed and unsigned integer multiplication and multiplication-accumulation, at the same time,this method improves operation speed and reduces the area. successfully simulated in Cadence EDA tools. |
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| Keywords: | Multiplier accumulator circuit Multiplier Pipeline |
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