Vertical MOS-gated pin-diodes: MOS-gated tunneling transistors in Si(100) and Si(111)

Tunneling devices are an interesting alternative to conventional MOS-devices due to their high speed switching capabilities. Recently, it was shown that tunneling transistors based on vertical MOS-gated pin-diodes can be fabricated. The pin-diodes themselves were grown by means of UHV-MBE on highly n⁺-doped Si(100)-substrates with a 100 nm thick intrinsic channel region. The top contact was formed by the deposition of a highly-doped B δ-layer with a peak doping amount of approximately 10²¹ cm⁻³ for the necessary abrupt pn-junction and 300-nm p⁺-contact region. At a low supply voltage of −0.2 V, a current gain of three orders of magnitude with saturation behavior is achieved [1]. In the present contribution, we have shown the influence of the amount of B in the δ-layer and of the abruptness of the drain-channel-junction on the transistor behavior. For that, we have discussed the characteristics of MOS-gated pin-diodes on Si(111) with ultra-sharp B δ's with a peak doping amount between 10²⁰ and 10²¹ cm⁻³ and a peak width <3 nm, in comparison with MOS-gated pin-diodes on Si(100) presented in Hansch et al. [1]. In order to obtain these highly doped ultra-sharp B δ-layers, a phase-transition from an electrically inactive Si(111)- -R30° B surface phase into an electrically active one was induced by rapid thermal annealing.