| 基于FPGA与GPSP的时统设备研发 |
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| 引用本文： | 廖瑛,聂桂根,贺喜,吴怀庆. 基于FPGA与GPSP的时统设备研发[J]. 计算机与数字工程, 2005, 0(6) |
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| 作者姓名： | 廖瑛 聂桂根 贺喜 吴怀庆 |
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| 作者单位： | 武汉大学GPS工程技术研究中心 武汉430079(廖瑛，聂桂根，贺喜)，安徽省巢湖市水利规划设计院 巢湖238000(吴怀庆) |
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| 基金项目： | 地球空间环境与大地测量教育部重点实验室开放研究基金项目(编号02-09-05) |
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| 摘 要： | 在系统设计中,高度集成的现场可编程门阵列可以通过编写软件的方法来实现硬件功能,具有电路简单、应用方便等优点。本文介绍了ALTERA公司的ACEX1K系列芯片,及其在基于GPS的时统设备中的应用。利用其ClockLock和ClockBoost电路保证了时钟脉冲延迟和相位差的减小、时钟倍频的实现。
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| 关 键 词： | 现场可编程门阵列(FPGA) GPS 时统设备 频率标准 |
Development in Timing Equipment Based on GPS Receiver and FPGA |
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| Abstract: | Highly integrated field programmable gate array completes hardware function with the method of editing software. In design of system, the circuit has an advantage of simple and convenience in application. In this paper, the ACEX 1K chips of ALTERA corporation and it's application in timing equipment based on GPS are introduced. By means of the ClockLock and ClockBoost circuitry, the clock delay and the skew within a device are reduced, and the clock multiplier is provided. |
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| Keywords: | field programmable gate array(FPGA) GPS timing equipment frequency standards |
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