| 基于FPGA的手持式数字示波器的设计 |
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| 引用本文： | 朱詠筠,易艺,郝建卫,李俊凯,王奕澄.基于FPGA的手持式数字示波器的设计[J].电子测量技术,2015,38(9):69-72. |
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| 作者姓名： | 朱詠筠 易艺 郝建卫 李俊凯 王奕澄 |
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| 作者单位： | 桂林电子科技大学信息科技学院电子工程系桂林541004,桂林电子科技大学信息科技学院电子工程系桂林541004,桂林电子科技大学信息科技学院电子工程系桂林541004,桂林电子科技大学信息科技学院电子工程系桂林541004,桂林电子科技大学信息科技学院电子工程系桂林541004 |
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| 基金项目： | 2014年广西壮族自治区级大学生创新创业训练计划立项（201413644013）项目 |
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| 摘 要： | 针对传统示波器体积大、携带不便等问题，利用现场可编程门阵列（field programmable gate array，FPGA）强大的性能，研制一款基于FPGA的手持式数字示波器。系统以Altera公司FPGA为主控芯片组建逻辑控制电路，利用Quartus II开发工具以及Verilog HDL语言描述控制逻辑，实现时钟分配、采样缓冲、触发、测频、测幅等功能。用SOPC Builder构建Nios II软核处理器，通过C语言编程实现触摸控制、显示控制等功能。经过实验测试表明，该示波器系统工作稳定，具有较高的性能指标和实用性，在手持式数字示波器的研制方面有较好的参考价值。
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| 关 键 词： | FPGA 数字示波器 Nios II ADS831 实时采样 |
Design of hand held digital oscilloscope based on FPGA |
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| Zhu Yongjun,Yi Yi,Hao Jianwei,Li Junkai and Wang Yicheng.Design of hand held digital oscilloscope based on FPGA[J].Electronic Measurement Technology,2015,38(9):69-72. |
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| Authors: | Zhu Yongjun Yi Yi Hao Jianwei Li Junkai and Wang Yicheng |
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| Affiliation: | Department of Electronic Engineering, Institute of Information Technology, Guilin University of Electronic Technology, Guilin, 541004,China,Department of Electronic Engineering, Institute of Information Technology, Guilin University of Electronic Technology, Guilin, 541004,China,Department of Electronic Engineering, Institute of Information Technology, Guilin University of Electronic Technology, Guilin, 541004,China,Department of Electronic Engineering, Institute of Information Technology, Guilin University of Electronic Technology, Guilin, 541004,China and Department of Electronic Engineering, Institute of Information Technology, Guilin University of Electronic Technology, Guilin, 541004,China |
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| Abstract: | According to the weakness of traditional oscilloscope problems such as large volume and inconvenience, the project base on FPGA (Field Programmable Gate Array) strong performance to develop a hand held digital oscilloscope. The system use Altera FPGA as the main control chip to design a logic control circuit. And it use the Quartus II development tools and Verilog HDL language to describe the functions such as control logic, clock distribution, sampling buffer, trigger, frequency and amplitude measuring, etc. System design the SOPC Builder to build the Nios II soft core processor, and it through the C language programming to realize the touch control, display control functions. The test result shows that the oscilloscope system work is stable, and it has high performance and practicality. The project has reference value in the research of the hand held digital oscilloscope. |
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| Keywords: | FPGA digital oscilloscope Nios II ADS831 real time sampling |
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