1. imec, , Leuven, B‐3001 Belgium;2. ESAT, Katholieke Universiteit Leuven, , Leuven, 3000 Belgium;3. Holst Centre, , Eindhoven, 5656 AE The Netherlands;4. Device Solutions Center, Panasonic Corporation, , Kadoma‐shi, 571‐8501 Japan
Abstract:
A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm2/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (ION/OFF) of >107. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 104 s. We achieve a stage‐delay of ~19.6 ns at VDD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (VDD), the brightness of the display exceeds 150 cd/m2.