| 新型带清零的半静态D触发器芯片设计 |
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| 引用本文： | 赵俊霞,朱巧艳.新型带清零的半静态D触发器芯片设计[J].电子世界,2012(7):147-149. |
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| 作者姓名： | 赵俊霞 朱巧艳 |
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| 作者单位： | 三江学院;南京拓微集成电路有限公司 |
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| 摘 要： | 为了提高D触发器的速度、降低功耗、缩小面积,本文对常用D触发器进行分析,综合各自优缺点,优化最高频率,设计出一款新型带清零的半静态D触发器,采用华润上华0.6μmN阱CMOS工艺,版图面积为46.500×40.350(μm)。该触发器的最高频率为356MHz,运用她构成二分频器并仿真成功。
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| 关 键 词： | D触发器 半静态 清零 版图 |
A New D flip-flop of semi-static and clear |
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| Zhao Junxia,Zhu Qiaoyan.A New D flip-flop of semi-static and clear[J].Electronics World,2012(7):147-149. |
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| Authors: | Zhao Junxia Zhu Qiaoyan |
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| Affiliation: | (Sanjiang College,Nanjing,Jiangsu 210012;NanJing Top Power ASIC) |
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| Abstract: | For faster speed、lower power and smaller size,this paper analyzes several used D flip-flops.For the highest frequency and synthesizing their advantages and disadvantages,we design a new type D flip-flop of semi-static and clear.With CSMC 0.6μmN well CMOS process,the layout area is46.500×40.350(μm).The maximum trigger frequency is 356MHz.Using it we constitute the second divider and simulates successfully. |
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| Keywords: | D flip-flop semi-static clear layout |
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