| 基于AMBA总线的AES算法设计 |
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| 引用本文： | 朱彬,刘新宁.基于AMBA总线的AES算法设计[J].电子工程师,2009,35(5):47-50. |
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| 作者姓名： | 朱彬 刘新宁 |
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| 作者单位： | 东南大学电子科学与工程学院,江苏省南京市,210096 |
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| 摘 要： | 描述了基于AMBA（高级微控制器总线架构）总线的AES（高级加密标准）算法硬件设计。AES算法采用状态机实现，具有4种工作模式、支持2种密钥以及AHB（高级高性能总线）。采用实验室的SEGPS平台对设计进行仿真验证，并与采用C＋＋语言实现的AES进行比对验证。最后，选用FPGA（现场可编程门阵列）进行综合，结果显示，可工作最高频率为140．1MHz，占用逻辑单元的资源为6977，数据吞吐率最高为351．65Mbit／s。
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| 关 键 词： | 加密 AES 状态机 AHB Verilog |
Design of AES Algorithm Based on AMBA |
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| ZHU Bin,LIU Xinning.Design of AES Algorithm Based on AMBA[J].Electronic Engineer,2009,35(5):47-50. |
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| Authors: | ZHU Bin LIU Xinning |
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| Affiliation: | Department of Electronic Science and Engineering;Southeast University;Nanjing 210096;China |
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| Abstract: | This paper presents a hardware design of AES algorithm based on AMBA. Our design, using the state machine, can configure four modes of AES operation with 128 bit, 192 bit cipher key. Furthermore, the interface between AHB and AES was also designed. Designed functionality was verified on SEGPS platform by comparing our results with the right data which were figured out by C＋＋ program. Finally, through synthesis, using the Stratix Ⅱ ES2S60F1020C4, it can operate up to 140.1 MHz, and uses 6 977 ALUTs. The maximum throughput of our design is 351.65 Mbps. |
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| Keywords: | AES AHB Verilog |
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