A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs |
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| Authors: | F. Azaïs S. Bernard Y. Bertrand M. Renovell |
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| Affiliation: | (1) Laboratoire d'Informatique Robotique Microélectronique de Montpellier (LIRMM), Université de Montpellier II: Sciences et Techniques du Languedoc, 161, rue Ada-34392, Montpellier Cedex 5, France |
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| Abstract: | This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry. |
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| Keywords: | analog and mixed-signal testing ADC test Built-In Self-Test (BIST) |
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