用遗传算法优化测试通路结构设计

嵌入核测试通路问题是片上系统设计中的重要问题，由于嵌入核与芯片的输入/输出管脚没有直接通路，因此需要设计专门的测试通路结构对它们进行测试，以减少测试时间，降低测试成本，提出一种基于遗传算法的优化算法来设计测试通路结构，并选取了两个假定的、比较复杂的片上系统作为例子，实验结果表明，文中算法搜索到全局最优解(或近似全局最优解)的能力优于现有的整数线性规划方法。

Optimizing Test Access Architecture by Genetic Algorithm

Test access is a main issue encountered in the core based system on chip (SOC) design For an embedded core, which is deeply embedded in the system chip, direct physical access to its peripheries is not available by default; hence, additional access mechanisms are required An approach based on genetic algorithm is proposed to deal with several issues related to the design of optimal test access mechanisms that minimize test time of SOC, including the assignment of cores to test buses, and distribution of test data width between multiple test buses As a case study, the test access mechanisms of two hypothetical but nontrivial systems are optimized by our approach Experiment results show that the proposed algorithm performs better in global optimum searching than the existing method based on integer linear programming (ILP)