HDLC协议RS-485总线控制器的FPGA实现

介绍了以HDLC协议控制为基础的RS-485总线通信控制器，采用VHDL语言在RTL级设计，并在单片FPGA上实现．该控制器具有两个独立的全双工通道，通过存储器管理单元共用片内4KB双口RAM，与CPU进行数据交换．内建中断管理模块，可以工作在查询模式或中断模式．CPU可通过内部ISA总线接口，对片内RAM地址、本站站址、收发数据长度、数据的波特率等编程控制．工作时钟为40MHz时，各通道波特率最高可达10MHz．实际应用表明，此控制器设计合理，工作可靠。

The Implement of RS-485 Bus Controller Based on HDLC Protocol by a Single FPGA Chip

An interface chip used as the RS485 bus controller based on HDLC protocol was introduced, which was written in VHDL at the RTL level and implemented by a single FPGA chip. The chip contains two full-dual transceivers independent of each other, performing the transmitting and receiving of synchronal series data. The chip exchanges data with CPU by a build-up 4K-bytes RAM, which was shared by both transceivers. An interrupt management module was also built in, it enables the interface to work on either query mode or interrupt mode. Many registers, such as the station address, the length of series data and the baud rate, etc., that controlling the chip's working status, can be set a value by CPU through an inner ISA interface. The interface chip has the characteristics of simple, flexible, and easy in use. It can be driven by 40 MHz clock signal and the transceivers can handle the series data at the maximum rate of 40M Hz. The application result shows that the interface chip is proper-designed and of high reliability.