| 基于FPGA的高速实时数据采集系统设计 |
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| 引用本文： | 张秋云,王黎,高晓蓉,王泽勇,郭建强.基于FPGA的高速实时数据采集系统设计[J].现代电子技术,2012,35(7):69-72,76. |
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| 作者姓名： | 张秋云 王黎 高晓蓉 王泽勇 郭建强 |
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| 作者单位： | 西南交通大学光电工程研究所,四川成都,610031 |
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| 摘 要： | 设计的基于FPGA的高速实时数据采集系统,可控制6路模拟信号的采集和处理,FPGA中的6个FIFO对数据进行缓存,数据总线传给DSP进行实时处理和上传给上位机显示。程序部分是用Verilog HDL语言,并利用QuartusⅡ等EDA软件进行仿真,验证了设计功能的正确性。
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| 关 键 词： | FPGA VerilogHDL FIFO 数据采集 |
Design of high speed real-time data acquisition system based on FPGA |
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| ZHANG Qiu-yun
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WANG Li
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GAO Xiao-rong
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WANG Ze-yong
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GUO Jian-qiang.Design of high speed real-time data acquisition system based on FPGA[J].Modern Electronic Technique,2012,35(7):69-72,76. |
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| Authors: | ZHANG Qiu-yun WANG Li GAO Xiao-rong WANG Ze-yong GUO Jian-qiang |
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| Affiliation: | (Photo-electronic Engineering Institute,Southwest Jiaotong University,Chengdu 610031,China) |
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| Abstract: | A high speed real-time data acquisition system based on FPGA is designed.The process of system is that six original analog signals are collected and processed,and stored in the FIFOs memories in the FPGA,then shifted to the DSP for real-time processing through the data bus,finally uploaded to the host display.The procedure is programed with Verilog HDL language and simulated with QuartusⅡ and other EDA software in order to verify the correctness of the design.Satisfactory results have been obtained. |
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| Keywords: | FPGA Verilog HDL FIFO data acquisition |
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