Ultra thin chips for miniaturized products

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. One key to miniaturization developed in the past was the use of unpackaged, bare dice. Saving the volume and weight of the package, significant reduction in footprint was achieved. A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC). The use of recent manufacturing methods allows to merge the SiP approach with a volumetric integration. Up to now, most of the systems utilize single- or double-sided populated system carriers. Embedding of passive components was a first step forward. A new challenge is to incorporate not only passive components, but active circuitry (IC's) and the necessary thermal management as well. Ultra thin chips (i.e. silicon dies thinned down to 50 m total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB's. Micro via technology allows to connect the embedded chip to the outer faces of the system circuitry. As an ultimate goal for microsystem integration, the embedding of optical and fluidical system components can be envisioned. This paper presents the first approach to embed thin silicon dies in to polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable box-of-bricks type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT BGA.The authors would like to thank the team of the 3D-CSP and the ChiP task force at IZM Berlin/Munich and TU Berlin as well as the colleagues from the PCB industry having supported this feasibility study with activity and discussion. Part of the work shown here is done in of the BMBF Project Systemintegration in polymere Schaltungsträger, No.02PP2051, co-ordinated by the FZK-PFT. The support is gratefully acknowledged.This paper was presented at the Conference of Micro System Technologies 2001 in March 2001