| 并行行旁路乘法器的设计与实现 |
| |
| 引用本文： | 商丽卫,刘耀军. 并行行旁路乘法器的设计与实现[J]. 微电子学与计算机, 2012, 29(8): 134-137 |
| |
| 作者姓名： | 商丽卫 刘耀军 |
| |
| 作者单位： | 1. 太原科技大学计算机科学与技术学院,山西太原,030024
2. 太原师范学院计算机科学与技术系,山西太原,030012 |
| |
| 基金项目： | 山西省重点学科专项基金项目-加权自动机在信息处理中的应用 |
| |
| 摘 要： | 为了进一步降低乘法器运算过程中的延迟,减少功耗,在行旁路乘法器的基础上进一步优化,提出一种并行行旁路(PRB)乘法器,并用有限状态机进行了实现.在行旁路的基础上,通过对乘数进行重新编码并行输出部分积,使乘法运算中产生的部分积数量减少,提高运算速度;利用有限状态机实现PRB乘法器,有效减少了电路中逻辑元件的数量,降低了功耗.在Quartus平台上进行的仿真表明PRB乘法器在整体性能上有较大的改善.
|
| 关 键 词： | 有限状态机 行旁路乘法器 PRB乘法器 |
A Design and Implementation of Parallel Row Bypassing Multiplier |
| |
| SHANG Li-wei,LIU Yao-jun. A Design and Implementation of Parallel Row Bypassing Multiplier[J]. Microelectronics & Computer, 2012, 29(8): 134-137 |
| |
| Authors: | SHANG Li-wei LIU Yao-jun |
| |
| Affiliation: | 1 Computer Science and Technology School,Taiyuan University of Science and Technology,Taiyuan 030024,China; 2 Department of Computer Science and Technology,Taiyuan Normal University,Taiyuan 030012,China) |
| |
| Abstract: | In order to reduce the delay and power during multiplying,a Parallel Row Bypassing(PRB) multiplier based on the row bypassing multiplier was designed in this paper.It can greatly reduce the number of partial products and the operating delay by recoding the multiplier and parallel outputting the partial products.For decreasing the logic units and reducing the power,the PRB multiplier was implemented by the finite state automaton.This design was simulated in Quartus,and the simulation result shows that the PRB multiplier has a great improvement in the whole performance. |
| |
| Keywords: | finite state automaton row bypass multiplier parallel row bypassing multiplier |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
