| 复杂指令集流水线系统设计 |
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| 引用本文： | 靳文兵,左琦. 复杂指令集流水线系统设计[J]. 微电子学与计算机, 2012, 29(4): 19-22 |
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| 作者姓名： | 靳文兵 左琦 |
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| 作者单位： | 1. 北京理工大学计算机学院,北京100081／北方自动控制技术研究所,山西太原030006
2. 北京理工大学计算机学院,北京,100081 |
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| 摘 要： | 摒弃传统流水线设计必须先将复杂指令集指令转化为精简指令集指令,然后再按照精简指令集实现流水线的方法.采用拓展的哈佛结构,设计新型指令流水线前端多指令缓冲和双指令指针,以及流水线中、后端双总线寄存器组和多端口数据存储器,优化指令流水线结构,实现高效率的复杂指令集指令流水线系统.设计从理论上解决了复杂指令集流水线实现的两个难点:寄存器和存储器读写冲突问题,以及流水线各阶段功能和任务划分.VHDL语言建模,用ModelSim和Xilinx仿真、测试,证明复杂指令集流水线系统设计可行.
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| 关 键 词： | 微处理器 复杂指令集 流水线 多端口存储器 读写冲突 |
Design of CISC Pipeline System |
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| JIN Wen-bing,ZUO Qi. Design of CISC Pipeline System[J]. Microelectronics & Computer, 2012, 29(4): 19-22 |
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| Authors: | JIN Wen-bing ZUO Qi |
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| Affiliation: | 1(1 School of Computer Science and Technology,Beijing Institute of Technology,Beijing 100081,China; 2 North Automatic Control Technology Institute,Taiyuan 030006,China) |
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| Abstract: | Design of pipeline without translation from CISC instructions to RISC instructions.Instruction buffers and caches are implemented in the front stage of CISC pipeline with double Program Counters pointing to opcode and operand separately.Multi-port registers and memories are designed to support simultaneously read and write by different stages.Optimization for pipeline functions is adopted in order to realize an effective CISC pipeline system.Final evaluation and test by ModelSim and Xilinx tool sets prove the design workable and preferable. |
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| Keywords: | microprocessor CISC Pipeline multi-port memory read-write conflict |
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