| LTE中卷积码的译码器设计与FPGA实现 |
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| 引用本文： | 李冬冬,LI Dong-dong. LTE中卷积码的译码器设计与FPGA实现[J]. 现代电子技术, 2011, 34(13): 46-48,52 |
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| 作者姓名： | 李冬冬 LI Dong-dong |
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| 作者单位： | 北京工业大学北京市嵌入式系统重点实验室,北京,100124 |
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| 摘 要： | 基于长期演进（LTE）的Tail—biting卷积码，介绍了维特比译码算法，它是一种最优的卷积码译码算法。由于Tail—biting卷积码的循环特性，采用固定延迟译码的方法，降低了译码复杂度。通过使用全并行的结构及简单的回溯存储方法，设计了一个具有高速和低复杂度的固定延迟译码器。在FPGA上实现并验证，验证结果表明译码器的性能满足了LTE系统的要求。
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| 关 键 词： | LTE Tail—biting卷积码 维特比译码算法 固定延迟译码 FPGA |
Design and FPGA Implementation of Decoder for Convolutional Code in LTE |
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| LI Dong-dong. Design and FPGA Implementation of Decoder for Convolutional Code in LTE[J]. Modern Electronic Technique, 2011, 34(13): 46-48,52 |
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| Authors: | LI Dong-dong |
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| Affiliation: | LI Dong-dong(Beijing Embeded System Key Lab,Beijing University of Technology,Beijing 100124,China) |
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| Abstract: | Based on Tail-biting convolutional code of LTE,Viterbi Algorithm which is a optimal decoding algorithm of convolutional codes is introduced.The fixed-delay decoding scheme is adopted to reduce the decoding complexity according to the circular property of Tail-biting convolutional code.By using all parallel structure and simple trace back memory method,a fixed-delay decoder with higher speed and lower complexity is designed.The decoder was implemented and verified with FPGA.The results of verification show t... |
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| Keywords: | LTE Tail-biting convolutional code Viterbi Algorithm fixed-delay decoding FPGA |
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