| 基于FPGA的DDS＋DPLL跳频信号源设计 |
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| 引用本文： | 杨红,李海,隆行.基于FPGA的DDS＋DPLL跳频信号源设计[J].现代电子技术,2011,34(15):101-104. |
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| 作者姓名： | 杨红 李海 隆行 |
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| 作者单位： | 电子科技大学成都学院微电子技术系,四川成都,611731 |
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| 摘 要： | 针对跳频通信系统有固有噪声的特点,结合DDS＋DPLL高分辨率、高频率捷变速度的优点,并采用Altera公司的Quartus-Ⅱ_10.1软件进行设计综合,提出了一种新型的跳频信号源。结果表明,该设计中DPLL时钟可达到120MHz,性能较高,而仅使用了30个LUT和18个触发器,占用资源很少。
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| 关 键 词： | 数字鉴相器 滤波器 数控振荡器 DPLL |
Design of DDS+PLL Frequency Hopping Signal Source Based on FPGA |
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| YANG Hong,LI Hai,LONG Hang.Design of DDS+PLL Frequency Hopping Signal Source Based on FPGA[J].Modern Electronic Technique,2011,34(15):101-104. |
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| Authors: | YANG Hong LI Hai LONG Hang |
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| Affiliation: | YANG Hong,LI Hai,LONG Hang(School of Microelectronics,Chengdu College,University of Electronic Science and Technology of China,Chengdu 611731,China) |
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| Abstract: | Since the frequency hopping（FH） communication system has the inherent noise characteristics,a new FH signal source is proposed in combination with high-resolution high-frequency agility advantages of DDS＋DPLL and Quartus-Ⅱ_10.1 software of Altera Company for design.Only 30 LUTs and 18 triggers are used in the design.The simulation results show that the designed DPLL clock is up to 120 MHz and its performance is high. |
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| Keywords: | digital phase discriminator filter DCO DPLL |
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