一种全新的无源超高频标签芯片架构设计

为降低标签芯片功耗和提高无源超高频射频识别(UHF RFID)系统的识读距离，提出了一种全新的UHF RFID标签芯片架构．基于该架构设计的芯片能够根据读写器发送的命令，自动同步提取解码时钟用于命令解析，同时，能够根据启动盘点周期的query命令中的TRcal的长度以及DR值，生成满足反向散射频率要求的时钟．生成的反向散射时钟频率与制造工艺及芯片工作环境无关，工作中无需校准．相比传统的基于高频率采样时钟的结构，该设计架构不需要产生全局的用于采样数据的高频时钟，以及为自适应调整反向散射频率而在基带所作的复杂的分频，因此具有电路规模小、整体功耗低的优点．采用TSMC 0.18μm mixed signal工艺下的库文件进行仿真以及最终流片，仿真以及测试结果表明，基于该架构的芯片电路在完成相同功能的前提下，电路的整体规模是传统结构的90％，功耗是传统结构的70％．

Novel structure design of the passive UHF RFID tag-chip

A novel structure for the passive UHF RFID tag-chip design is presented for reducing the chip power-consumption and increasing the system operating distance. The tag-chip designed based on the new structure can automatically and synchronously recover the decoding clock out of the data sent from the interrogator and can well generate the backscatter link clock with the values of TRcal and DR specified in the query command that initiates an inventory round. The backscatter link clock frequency has no connection with manufacturing technology and chip working conditions, so it needs no calibration during operation. Since there are no requirements of high frequency sampling-clock or complex frequency-division circuits, which are necessary for conventional structure, the proposed structure is characterized by a smaller circuits scale and lower power-consumption. The chip is designed and fabricated using the TSMC 0.18μm mixed signal process. Simulation and test results show that the new structure is ten percent smaller in area and thirty percent lower in power comsumption.