基于反馈约束的SRAM接口时序分析方法

FPGA验证作为保证FPGA产品功能和可靠性的重要手段已经备受关注。对接口芯片时序的验证通常通过布局布线后仿真来进行,但布局布线后仿真需要耗费大量的时间。本文介绍了一种基于反馈的SRAM接口时序验证的方法,将FPGA输入输出连接成一个回路,验证结果表明,与动态仿真验证相比,该种静态时序验证方法可以较早、快速、精确定位FPGA接口时序设计存在的问题。缩短了验证时间,提高了验证效率、准确性和覆盖率。

SRAM Interface Timing Analysis Method Based On Feedback Constraint

FPGA verification has attracted much attention as an important means of FPGA product function and reliability. Verification of interface timing is usually done by post-layout simulation, but simulation after layout and routing takes a lot of time. This paper introduces a method of timing verification of SRAM interface based on feedback constraint, which links the input and output of FPGA, the verification results show that compared with dynamic simulation, this static timing verification method can locate the problems in timing design of FPGA interface earlier, faster and more accurately. It shortens the verification time and improves the verification efficiency and coverage.