基于高速采样的实时DDC架构技术

近年来，随着混合域示波器技术的发展，示波器既要实现传统示波器的功能，又要实现频域、调制域功能，这样在数字域信号处理中需要实现实时数字下变频（DDC）功能，实时DDC技术是实现示波器向频域和调制域功能扩展的基础，可以实现示波器的增值应用，大大扩大示波器的应用领域。本文根据高速信号采样的特点，给出了实时DDC技术架构，该架构由数字正交混频、FIR1-FIR3滤波器、HB1-HB10滤波器组成，对于20GSa/s采样数据流而言，最高支持1.25GSa/s I/Q数据流输出，最低305 kSa/s I/Q数据流输出，可满足绝大多数应用场景。对数字正交混频、FIR1滤波器、FIR2滤波器、FIR3滤波器、HB滤波器进行详细设计分析，给出了实现架构，对于FIR和HB滤波器，还给出了最佳滤波器阶数及其幅频响应曲线。对于数字正交混频、FIR1-FIR3滤波器，由于其数字速率超过了FPGA正常工作时钟范围，通过多路并行处理的手段实现信号处理。最后使用矢量信号分析软件对DDC的13种I/Q速率下的EVM性能进行了评估，分别评估了载波频率1.5GHz和3GHz的EVM性能，通过评估，EVM值大部分集中在0.5%以下，可满足使用需求。

Real-time DDC Architecture TechnologyBased on High-speed Sampling

In recent years, with the development of hybrid domain oscilloscope technology, the oscilloscope not only realizes the function of traditional oscilloscope, but also the function of frequency domain and modulation domain. So it is necessary to realize the function of real-time digital down-conversion (DDC) in digital domain signal processing. Real-time DDC technology is the basis of extending the function of oscilloscope to frequency domain and modulation domain. The value-added application of oscilloscope can be realized, and the application field of oscilloscope can be greatly expanded. According to the characteristics of high-speed signal sampling, this paper presents a real-time DDC technology architecture, which consists of digital orthogonal mixing, FIR1-FIR3 filter and HB1-HB10 filter. For 20GSa/s sampled data stream, the maximum support is 1.25GSa/s I/Q data stream output and the minimum 305 kSa/s I/Q data stream output, which can satisfy most application scenarios. Then, the digital orthogonal mixing, FIR1 filter, FIR2 filter, FIR3 filter and HB filter are designed and analyzed in detail, and the implementation architecture is given. For FIR and HB filters, the optimal filter order and its amplitude-frequency response curve are also given. For digital orthogonal mixer and FIR1-FIR3 filter, signal processing is realized by means of multi-channel parallel processing because its digital rate exceeds the normal working time range of the FPGA. Finally, the EVM performance of DDC at 13 I/Q rates is evaluated by vector signal analysis software. The EVM performance of carrier frequencies of 1.5 GHz and 3 GHz is evaluated respectively. Through the evaluation, the EVM value is mostly concentrated below 0.5%, which can meet the needs of application.