| 基于边界元法的二维VLSI版图电容提取 |
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| 引用本文： | 胡庆生,林争辉.基于边界元法的二维VLSI版图电容提取[J].微电子学,1997,27(4):267-271. |
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| 作者姓名： | 胡庆生 林争辉 |
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| 作者单位： | 上海交通大学大规模集成电路研究所 |
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| 摘 要： | 提出了一种用边界元法计算ＶＬＳＩ版图电容的方法，通过求解二维拉普拉斯方程，直接得到版图中各种类型的电容的值。该方法提取数据准确简单，占用内存少，计算效率高，且有较高的精度。用该方法对几种典型的ＶＬＳＩ版图电容进行提取，均取得较好的结果。
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| 关 键 词： | 边界元法 VLSI 参数提取 电容矩阵 |
A 2-D Capacitance Extractor for VLSI Layout Using Boundary Element Method |
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| HU Qing-Sheng and I-IN Zheng-Hui LSl Research Institute,Shanghai Jiaotong University Shanghai.A 2-D Capacitance Extractor for VLSI Layout Using Boundary Element Method[J].Microelectronics,1997,27(4):267-271. |
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| Authors: | HU Qing-Sheng and I-IN Zheng-Hui LSl Research Institute Shanghai Jiaotong University Shanghai |
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| Affiliation: | HU Qing-Sheng and I-IN Zheng-Hui LSl Research Institute,Shanghai Jiaotong University Shanghai 200030 ) |
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| Abstract: | A two-dimensional (2-D) extraction of capacitance for VLSl layout using boundary el-ement method is given in this paper. By solving 2-D Lap1ace equation, various capacitances includ- ing parasitic capacitance are obtained. Compared with other methods, the extractor can not only prepare the input data with ease, but also has high efficiency and accuracy. Calculated results from some examples using theproposed extractor show good agreement with the experimental data- |
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| Keywords: | VLSI Parameter extraction Capacitance matrix Boundary element method EEACC 2130 2570A |
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