32位微处理器总线接口部件的设计

由于微处理器和存储器两者之间速度的差异性，存储系统已经成为提高微处理器性能的一个瓶颈。同时，系统总线的开销在整个访存延迟中占有相当大的比重。因而，设计一个高效的总线接口对于提高微处理器的性能是非常重要的。文中在32位微处理器ARS03总线接口部件的设计中，使用Load／Store缓冲模型和流水、乱序执行的地址、数据总线等方法来提高其效率，采用M／M／1／K排队论模型确定了缓存队列的长度。实际应用程序仿真结果表明，总线接口的设计是高效的，去掉使用的优化方法会使ARS03的执行时间平均增加21．6％。

On Designing for Chinese Use a BIU (Bus Interface Unit)of a 32-bit RISC

The Aviation Microelectronic Center of NPU(Northwestern Polytechnical University) has recently completed the development of a 32-bit super-scalar RISC microprocessor, which we call ARS03(Advanced RISC System 03), for filling the need of Chinese military aviation. In this paper, we present the design of the BIU of ARS03, which we deem to be successful because it helps ARS03 to meet performance requirements. Fig.1 gives the schematical diagram of the architecture of ARS03. Section 2 explains in detail the design of its BIU. Subsection 2.1 explains the BIU's processing logic. Subsection 2.2 explains the two parts of BIU's buffer separately: output FIFO(First In First Out) in subsubsection 2.2.1 and input FIFO in subsubsection 2.2.2. In connection with output FIFO, we stress that, from the buffer full probabilities calculated by us for different queue lengths and presented in Table 1, we select 8 as the suitable value for queue length K. Subsections 2.3 and 2.4 explain respectively the BIU's snoop logic and control path. After embedding our BIU into ARS03, we evaluated ARS03's performance with five application programs of avionics. Simulation results, as shown in Fig.4, indicate that our design of BIU, as compared with traditional design of BIU, can reduce ARS03's execution time by 17.8% as an average.