A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation |
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Authors: | Muhammad Bashir Linda Milor |
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Affiliation: | aSchool of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, United States |
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Abstract: | Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45 nm technology test chip to relate geometry to failure rate statistics. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to account for die-to-die linewidth variation when determining if low-k materials satisfy lifetime requirements. |
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