| 基于低摆幅互连线的NoC功耗降低技术 |
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| 引用本文： | 李媛媛,齐跃. 基于低摆幅互连线的NoC功耗降低技术[J]. 武汉理工大学学报, 2012, 34(2): 135-139 |
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| 作者姓名： | 李媛媛 齐跃 |
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| 作者单位： | 1. 武汉理工大学计算机科学与技术学院,武汉,430070
2. 江苏顺天海运集团有限公司,南京,210016 |
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| 基金项目： | 国家自然科学基金(60572015) |
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| 摘 要： | 在高性能的片上系统设计中,功耗已经成为制约片上网络发展的重要约束。首先用混合插入方法计算了全局芯片网络中各条路径的延时和功耗。相比起用最优中继驱动器插入方法,这种情况下互连线的延时和功耗分别降低了24.36%和11.81%。在混合插入方法的基础上进行优化后,相比起用混合插入方法,互连线功耗降低了21.75%。
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| 关 键 词： | 片上网络 低摆幅互连 低功耗 延时 |
Power Reducing Technology of Network-on-chip Based on the Low-swing Interconnect |
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| LI Yuan-yuan , QI Yue. Power Reducing Technology of Network-on-chip Based on the Low-swing Interconnect[J]. Journal of Wuhan University of Technology, 2012, 34(2): 135-139 |
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| Authors: | LI Yuan-yuan QI Yue |
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| Affiliation: | 1.School of Computer Science and Technology,Wuhan University of Technology,Wuhan 430070,China; 2.Jiangsu SUNTY Shipping Group Co Ltd,Nanjing 210016,China) |
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| Abstract: | In the high-performance SoC design,power consumption becomes the main design constraint of NoC.In this paper,the author computes each path’s latency and power using hybrid insertion strategy first.In this case,the latency and power of interconnect are reduced by 24.36% and 11.81% than optimized repeater insertion,respectively.After the approach being optimized,the power of global interconnects has a reduction of 21.75% compared with HI strategy. |
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| Keywords: | network on chip low-swing interconnect low power delay |
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