A reconfigurable analog processor using coarse-grained,heterogeneous configurable analog blocks for field programmable mixed-signal processing |
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Authors: | Wen-Hui Fu Jun Jiang Xi Qin Ting Yi Zhi-Liang Hong |
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Affiliation: | (1) State Key Laboratory of ASIC and System, Fudan University, Shanghai, People’s Republic of China |
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Abstract: | A field programmable analog array (FPAA), designed for a reconfigurable analog processor, introduces coarse-grained, heterogeneous
configurable analog blocks that improves performance and power consumption. Designed in an SMIC standard 0.18 μm CMOS process,
mixed-signal processing can be performed by the assistance of an on-chip MCU and configurable digital blocks. Relative precision
of the analog processing is 99.5%. A PID controller is shown as an application example. With a total die area of 11 mm2, the maximum power consumption is 17.6 mA with a 3.3 V supply voltage, resulting in a 17× improvement in energy-efficiency
over current conventional FPAAs. |
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Keywords: | |
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