Current-mode algorithmic analog-to-digital converters

A current-mode technique for the design of algorithmic analog-to-digital converters (ADCs) is presented. The current-mode technique allows the necessary voltage swing for a given dynamic range to be reduced while at the same time eliminating the need for large capacitors on which to store the signal. Consequently, the resulting ADCs can be made very small and yet still capable of providing high sampling rates. The advantages and disadvantages of different current mirror structures for use in ADCs are discussed. Experimental results for ADCs fabricated using a 3-μm CMOS process are reported, including an 8-b ADC which displayed a sampling rate of 500 kHz and a total circuit area of under 0.75 mm²