New CMOS four-quadrant multiplier and squarer circuits |
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| Authors: | Shen-Iuan Liu Cheng-Chieh Chang Yuh-Shyan Hwang |
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| Affiliation: | (1) Department of Electrical Engineering, National Taiwan University, 10664 Taipei, Taiwan R.O.C.;(2) Department of Electronic Engineering, National Taiwan Institute of Technology, 10672 Taipei, Taiwan R.O.C. |
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| Abstract: | A CMOS four-quadrant multiplier and a squarer using the positive feedback loops consisting of the current mirrors are presented. Simulation results are given to verify the theoretical analysis. The input range of this multiplier is over ±2.5V with the linearity error less than 1% and its-3dB bandwidth is about 20MHz. The total harmonic distortion is less than 1% with the input range up to ±2V. The squarer has a ±1.6V input range. Second order effects such as mobility reduction and transistor mismatch have been discussed. Experimental results by using discrete components are also given. The proposed circuits are expected to be useful in analog signal-processing applications. |
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