| 基于FPGA的线性可变码位控制全数字锁相环的设计与仿真 |
| |
| 引用本文： | 单长虹,邓国扬,孟宪元.基于FPGA的线性可变码位控制全数字锁相环的设计与仿真[J].计算机仿真,2003,20(2):111-113,74. |
| |
| 作者姓名： | 单长虹 邓国扬 孟宪元 |
| |
| 作者单位： | 1. 南华大学电气工程学院,湖南,衡阳,421001
2. 清华大学电子工程系,北京,100084 |
| |
| 摘 要： | 线性可变码位控制全数字锁相环（LVBC－DPLL）具有环路捕捉时间快的特点，该文介绍了以EDA技术作为开发手段的LVBC－DPLL的设计与实现，并分析了系统的稳态性能及仿真结果。
|
| 关 键 词： | FPGA 线性可变码位控制 全数字锁相环 设计 仿真 |
| 文章编号： | 1006-9348(2003)02-0111-03 |
Design and Simulation for the Digital Phase-Locked Loops with Linear Variable Bits Control Based on FPGA |
| |
| SHAN Chang-hong ,DENG Guo-yang ,MENG Xian-yuan.Design and Simulation for the Digital Phase-Locked Loops with Linear Variable Bits Control Based on FPGA[J].Computer Simulation,2003,20(2):111-113,74. |
| |
| Authors: | SHAN Chang-hong DENG Guo-yang MENG Xian-yuan |
| |
| Affiliation: | SHAN Chang-hong 1,DENG Guo-yang 1,MENG Xian-yuan 2 |
| |
| Abstract: | The digital phase-locked loops with linear variable bits control(LVBC- DPLL) have the features of fast catch in loop. This article introduces the desig n and implementation of LVBC-DPLL with EDA. Its performance of stable state and simulation results are also analyzed. |
| |
| Keywords: | VHDL linear variable bit control DPLL FPGA Simulation |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
