| Abstract: | Scaling down methods have been shown to be attractive for IC optimization [8]. The IC yield degradation, which is observed in this process, is determined by adjustment of technological parameters based on the scaled circuits topology. After scaling down the topology the nominal point reoptimization procedure for the circuit is required. The application of the technological centering method [1] is proposed in this paper for solving this problem. The experimental verification of the presented procedure is shown in the conclusion. |
