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| 由E1生成H-MVIP总线的FPGA实现 | |
| 引用本文： | 王津涛,苏红,薄连安.由E1生成H-MVIP总线的FPGA实现[J].小型微型计算机系统,2006,27(8):1585-1587. |
| 作者姓名： | 王津涛 苏红 薄连安 |
| 作者单位： | 1. 南开大学,信息学院,天津,300071 2. 南开大学,信息学院,天津,300071;天津光电集团有限公司,天津,300211 3. 天津光电集团有限公司,天津,300211 |
| 基金项目： | 天津市自然科学基金项目（023600211）资助 |
| 摘 要： | 介绍了用FPGA如何实现由E1生成H—MVIP（High Density Multi—Vendor Integration Protocol）总线数据的过程．整个设计包括2．048MHz同步时钟的提取、HDB3解码、前置缓存和总线生成几部分，设计中利用VHDL高级硬件描述语言编程．以专门的EDA软件为开发环境经过仿真、综合、布局布线几个过程的反复，最后用Xilinx公司FPGA实现硬件功能． |
| 关 键 词： | H—MVIP E1 VHDL FPGA |
| 文章编号： | 1000-1220（2006）08-1585-03 |
| 收稿时间： | 05 23 2005 12:00AM |
| 修稿时间： | 2005-05-23 |
Generated H-MVIP Bus with E1 And its FPGA Realization |
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| WANG Jin-tao,SU Hong,BO Lian-an.Generated H-MVIP Bus with E1 And its FPGA Realization[J].Mini-micro Systems,2006,27(8):1585-1587. | |
| Authors: | WANG Jin-tao SU Hong BO Lian-an |
| Affiliation: | 1.Information Institute of Nankai University, Tianjin 300071, China;2.Tianjin Optical Electrical Group Co. ,LTD. , Tianjin 300211, China |
| Abstract: | Provided a kind of design idea that can produce the H-MVIP bus data coming from the El. The design includes 2. 048MHz synchronous clock generator, HDB3 eneoder, buffer and H-MVIP bus generator. The design uses the VHDL as the program language, the EDA tools as the development environment. The right program file is gotten by repeating several proeess of simulation synthesis layout and route. The Xilinx FPGA is used to realize function. |
| Keywords: | H-MVIP E1 VHDL FPGA |
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