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Cyclic Intersymbol Interference of Frequency-Domain Decision-Feedback Equalizer: Effect and Mitigation
Authors:Rih-Lung Chung  Jeng-Kuang Hwang
Affiliation:(1) Communication Signal Processing Laboratory, Department of Communication Engineering, Yuan-Ze University, 32026 Taipei, Taiwan
Abstract:This paper investigates an inherent but adverse phenomenon called cyclic intersymbol interference (cyclic ISI) occurred in frequency-domain decision-feedback equalizer (FD-DFE). The cyclic ISI is due to the cyclic-prefix insertion and modulo operation of the time-domain feedback filter. To analyze and further mitigate this problem, we first formulate the FD-DFE signal model in a compact and insightful vector-matrix form, which allows an efficient derivation of the MMSE receiver coefficients. Then, by viewing the bit-error-rate profile (BERP) with respect to different starting symbol position within a symbol block, it is shown that those leading data symbols suffer more from the cyclic-ISI effect and lead to a high error floor. Seeing this, a novel FD-DFE receiver structure, called P2B-FD-DFE (parallel-two-branch FD-DFE) receiver, is proposed to overcome this problem without sacrificing spectral efficiency. It consists of two parallel cooperating branches of almost identical FD-DFE receivers designed for different cyclic decision delays. Under severe cyclic-ISI circumstances, the receiver performance can be further improved by using (1) a larger block size, and/or (2) a cascade of multiple feedback stages. Simulation results demonstrate that, in severe ISI channel, while the conventional FD-DFE exhibits a very high error floor, our proposed receiver can almost completely suppress the cyclic-ISI effect. Rih-Lung Chung was born in Taoyuan, Taiwan R.O.C. He received the B.S. degree and finished the M.S. courses both in electrical engineering from Yuan-Ze University, Taiwan R.O.C., in 1998 and 1999, respectively. Now he is working on his doctoral degree. His research interests include digital communication, statistical signal processing, and channel estimation/equalization, especially for wireless communication system. Jeng-Kuang Hwang was born in Taipei, Taiwan, in 1962. He received the Ph.D. degree in electrical engineering from the National Tsing-Hua University, Hsin-Chu, Taiwan, in 1991. Currently, he is an associate professor with the Communication Engineering Department at Yuan-Ze University, Chung-Li, Taiwan. In 1997, he had been a visiting professor at AT&T Labs/Research, Redbank, NJ, doing researches on smart antennas for wireless communications. He has published over 70 journal and conference papers, and hold one US patent. His current research interests include communication and statistical signal processing, smart antennas, software-defined radios, VLSI signal processing, and power line communications.
Keywords:block transmission  cyclic intersymbol interference (cyclic ISI)  frequency-domain decision-feedback equalizer (FD-DFE)  cyclic decision delay
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