高性能容错处理核心的研究

本文提出了以三模冗余表决为基础构造容错处理核心的方案。三个ＣＰＵ模块采取松散同步的形式，只有在发生总线操作时才进行同步表决。在处理核心中采用了两级故障检测机制，以三模表决器作为第一级来保证处理核心有足够高的故障覆盖率；以ＣＰＵＡ模块的自检作为第二级来弥补表决器发现故障延迟的不足，缩短故障的潜伏时间。在表决器的设计中采取了表决器旁路及先编码、后表决的方法。先用编码的方式提取需要表决的数据的特征，然后

THE RESEARCH OF HIGH PERFORMANCE FAULT- TOLERANT PROCESSING CORE

The article presents the scheme based on Triple Modular redundant voting to construct the fault - tolerant processing core. Three CPU modules are loose synchronizations. They synchronize and then vote only when there is bus operation. In the processing core, the author uses two levels of fault detecting mechanism. The Triple Modular voter is the first level to promise the processing core will have enough high fault coverage rate. The CPU module's self- test is the second level,and its function is to find fault earlier and reduce the fault's latent time.The voter is designed on the side road and the data is first encoded and then voted. After extracting the signature of the data, the signature codes will be voted. The CPU module' s fault is detected in no - disturb way for the first time with the advanced boundary scan technology.