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面向固件代码分析的虚拟指令集体系结构设计
引用本文:赵远,曾光裕,王炜,崔晨,高洪博. 面向固件代码分析的虚拟指令集体系结构设计[J]. 计算机工程, 2012, 38(9): 271-274
作者姓名:赵远  曾光裕  王炜  崔晨  高洪博
作者单位:解放军信息工程大学信息工程学院,郑州,450002
基金项目:国家“863”计划基金资助项目(2009AA01Z434)
摘    要:传统虚拟指令集体系结构不能同时满足简单性和高效性的要求。为此,提出一种面向固件代码分析的虚拟指令集体系结构构造方法。设计多目标固件代码分析平台,在可配置虚拟硬件结构的基础上,获取最小完备指令集,并说明扩展虚拟指令集的方法。实验结果表明,该方法能降低翻译代码膨胀率,目标指令模拟时间比传统方法减少19%~35%。

关 键 词:固件代码  虚拟指令集体系结构  翻译代码膨胀率  最小完备指令集  虚拟硬件
收稿时间:2012-01-06

Design of Virtual Instruction Set Architecture for Firmware Code Analysis
ZHAO Yuan , ZENG Guang-yu , WANG Wei , CUI Chen , GAO Hong-bo. Design of Virtual Instruction Set Architecture for Firmware Code Analysis[J]. Computer Engineering, 2012, 38(9): 271-274
Authors:ZHAO Yuan    ZENG Guang-yu    WANG Wei    CUI Chen    GAO Hong-bo
Affiliation:(Institute of Information Engineering,PLA Information Engineering University,Zhengzhou 450002,China)
Abstract:For traditional Virtual Instruction Set Architecture(V-ISA) can not satisfy both brevity and high-efficiency well,this paper proposes a Virtual Instruction Set Architecture(V-ISA) design method for firmware code analysis.A muti-target firmware code analysis platform is designed,and on the basis of virtual hardware configuration that can be configured,a method for developing virtual instruction set is proposed that it first build the minimal complete instruction set and then expands it.Experimental result shows that this method can reduce translated-code expansion rate and get the simulation costs have a reduction of 19%~35% compared with the conventional one.
Keywords:firmware code  Virtual Instruction Set Architecture(V-ISA)  translated-code expansion rate  minimal complete instruction set  virtual hardware
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