Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology

This paper uses a CAD methodology proposed by the authors to design a low-power second-order ΣΔM. This modulator has been fabricated in a 0·7 μm CMOS technology to be used as the front-end of an energy-metering mixed-signal ASIC and features 16·4 bit at a digital output rate of 9·6 kHz with a power consumption of 1·71 mW. It yields a value of the power(W)/(2^{Resolution(bit)}×output rate (Hz)) figure which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies. © 1997 by John Wiley & Sons, Ltd.