A circuit implementation of a single-bit CMOS adder

In this article, a circuit implementation of a single-bit CMOS adder with enhanced performance is presented. The adder circuit consists of separate circuits operating in-parallel for obtaining the output sum and carry signals. The carry circuit signal is not used to form the sum signal. The sum signal circuit is a sequential connection of two XOR cells. The circuit operability is confirmed by the results of circuit simulation using Cadence Design Systems’ software.