基于JTAG的片上调试器与调试系统的设计实现

提出了一种基于JTAG协议的嵌入式CISC处理器的调试系统的设计方案。针对自主研发的教学用JU-C2型处理器设计了片上调试器和CPU内部寄存器扫描链，为构成一个完整的调试系统，还设计了USB-JTAG协议转换器和PC机控制软件。调试系统可以实现微指令级和机器指令级的单步、断点以及CPU内部寄存器值的查看和PC（程序计数器）写入，还有CPU的运行停止和复位这些常用的调试功能。分别介绍了系统的各个组成部分以及它们的原理，进行了系统测试，验证系统工作的正确性。调试系统对CPU内部数据通路侵入性较小，在教学中也有一定的实用性。

Design of on-chip-debugger and debug system based on JTAG

A design scheme of debug system for embedded CISC processor based on JTAG protocol is put forward. A OCD(On-Chip-Debugger)is designed for JU-C2 processor which is a self-development processor used on teach- ing. USB-JTAG protocol convertor, control console on PC and self-build data scan chaining in CPU are also designed, which finally composes a complete debug system. The debug system can implement microinstruction and machine instruction step debug, breakpoint debug, processor internal registers examine and PC write, moreover, processor run/stop and reset commonly used debug function. It respectively introduces the system components and their principles, then tests the system to verify the correctness of the system work.The debug system is less invasive for the CPU internal data path, and has a certain degree of practicality in teaching.