| 10Gb/s CMOS时钟和数据恢复电路的设计 |
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| 引用本文： | 陈莹梅,王志功,赵海兵,章丽,熊明珍.10Gb/s CMOS时钟和数据恢复电路的设计[J].固体电子学研究与进展,2005,25(4):494-498. |
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| 作者姓名： | 陈莹梅 王志功 赵海兵 章丽 熊明珍 |
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| 作者单位： | 东南大学射频和光电集成电路研究所,南京,210096;东南大学射频和光电集成电路研究所,南京,210096;东南大学射频和光电集成电路研究所,南京,210096;东南大学射频和光电集成电路研究所,南京,210096;东南大学射频和光电集成电路研究所,南京,210096 |
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| 基金项目： | 国家863计划项目（No.2002AA312230）资助课题 |
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| 摘 要： | 介绍了利用0.18μmCMOS工艺实现了应用于光纤传输系统SDHSTM-64级别的时钟和数据恢复电路。采用了电荷泵锁相环(CPPLL)结构,CPPLL中的鉴相器能够鉴测相位产生超前滞后逻辑,采样数据具有1∶2分接的功能。振荡器采用全集成LC压控振荡器,鉴相器采用半速率的结构。对应于10Gb/s的PRBS数据(231-1),恢复出的5GHz时钟的相位噪声为-112dBc/Hz@1MHz,同时10Gb/s的PRBS数据分接出两路5Gb/s数据。芯片面积仅为1.00mm×0.8mm,电源电压1.8V时功耗为158mW。
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| 关 键 词： | 时钟和数据恢复 LC压控振荡器 电荷泵锁相环 |
| 文章编号： | 1000-3819（2005）04-494-05 |
| 修稿时间： | 2005年4月11日 |
A 10 Gb/s CMOS Clock and Data Recovery Circuit |
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| CHEN Yingmei,WANG Zhigong,ZHAO Haibing,ZHANG Li,XIONG Mingzheng.A 10 Gb/s CMOS Clock and Data Recovery Circuit[J].Research & Progress of Solid State Electronics,2005,25(4):494-498. |
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| Authors: | CHEN Yingmei WANG Zhigong ZHAO Haibing ZHANG Li XIONG Mingzheng |
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| Abstract: | This paper introduces the design of a 10 Gb/s clock and data recovery circuit to be fabricated in 0.18 μm CMOS technology. The circuit is to be used in the SDH STM-64 optical communication system. This paper adopts the Charge Pump Phase-Locked Loops(CPPLL) scheme. The phase detector in CPPLL can detect the phase generating early-late phase logic and its special function is to sample the data to act as a 1∶2 demultiplexer.Employing a full integrated LC oscillator and a half rate PD, the recovered 5 GHz clock has a phase noise of -112 dBc/Hz at 1 MHz offset in response to 10-Gb/s PRBS input data(2 31-1).The 10-Gb/s PRBS data have been demultiplexed to two 5-Gb/s data.The 1.00mm×0.8 mm IC consumes 158 mW under a single 1.8 V power supply. |
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| Keywords: | Clock and Data Recovery(CDR) LC Voltage Controlled Oscillator(VCO) Charge Pump Phase-Locked Loops(CPPLL) |
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