Performance analysis of sub 10 nm regime source halo symmetric and asymmetric nanowire MOSFET with underlap engineering |
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| Authors: | Kumar P. Kiran Balaji B. Rao K. Srinivasa |
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| Affiliation: | 1.Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation(Deemed To Be University), Green Fields, Vaddesawaram, Guntur, 522502, Andhra Pradesh, India
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| Abstract: | Silicon - In this paper, we are proposing a gate oxide stack source halo symmetric and asymmetric underlap extension nanowire MOSFET with HfO2 spacer at 10 nm regime. The increased doping... |
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