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Buried Metal Silicon-on-Insulator Junctionless Transistor for Low Power CMOS Logic Circuits |
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| Authors: | Tiple Kaustubh K Patil Ganesh C |
| Affiliation: | 1.Center for VLSI and Nanotechnology, Visvesvaraya National Institute of Technology, Nagpur, 440010, India ; |
| Abstract: | Silicon - This paper deals with an innovative structure of silicon-on-insulator junctionless transistor (SOIJLT) by incorporating a buried metal layer of proper work-function which creates the... |
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