A real-time industrial pattern classification system |
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| Authors: | Khalaf S Zhu M Siy P Abdelguerfi M |
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| Affiliation: | Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI; |
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| Abstract: | Using the partitioned matrix approach, a parallel hardware architecture for a parametric (Bayes) classifier is designed. The architecture consists of simple, regularly structured processing elements operating in parallel. As a result, the proposed design is suitable for VLSI implementation. A comparative analysis shows that the approach is more efficient and can significantly reduce the cost required for implementing the classifier, while maintaining high speed |
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